Author: Gopinath Karmakar, Amol Wakankar, Ashutosh Kabra
Binding Type: Paperback
Publisher: Springer
Published: 10/11/2023
Pages: 360
Weight: 1.18lbs
Size: 9.21h x 6.14w x 0.79d
ISBN: 9783031279003
2023 Edition

About the Author

Gopinath Karmakar is a Scientific Officer-H in the Bhabha Atomic Research Centre (BARC) in Mumbai, India. He has nearly 35 years of experience in the field of instrumentation and control for safety-critical systems in nuclear power plants and nuclear research reactors, which includes the development of hard real-time systems, operating systems for safety-critical applications, software engineering for Class IA and IB systems, programmable controllers and systems engineering. He is also an adjunct faculty in BARC Training School.

Amol Wakankar has been working with BARC as a Scientific Officer since 2006. Amol has been focusing on safety critical systems development for nuclear power plants for more than 15 years. His field of expertise include analysis and compilation of synchronous dataflow programs and the application of formal methods in safety critical domains. His current research interests include the application of formal methods for architecture-centric dependability analysis and automated synthesis from formal requirements. Together with Paritosh Pandya, he has developed the DCSYNTH tool, which offers automatic synthesis of robust controllers and runtime enforcement shields.

Ashutosh Kabra has been working as a Scientific Officer at Bhabha Atomic Research Centre (BARC) since 2007. He has over a decade of experience in the development of computer based I&C systems for nuclear power plants and research reactors. His expertise includes embedded software development, formalization of PLC programming languages, system dependability analysis and software qualification. His current research activities are targeted at reliability analysis using systems architecture, distributed systems in safety-critical applications and formal verification of software.

Paritosh Pandya is an adjunct professor at IIT Bombay and former Dean of the School of Technology and Computer Science at the Tata Institute of Fundamental Research (TIFR). He is known for his work on Duration Calculus and the tools he developed, which include DCVALID, a validity and model checker, and DCSYNTH for automatic synthesis of robust controllers. Paritosh is the recipient of the prestigious IEEE RTS 2020 "Test of Time award" for his pioneering contributions to the theory of schedulability in hard real-time systems.